Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More Synopsys announced its plans for expanding its processor intellectual ...
T2M-IP, a global semiconductor IP provider and ASIC services partner, today announced the global availability of its complete RISC-V CPU IP portfolio, spanning ultra-low-power MCU-class cores to ...
At least that’s the idea behind the Bit-Brick Cluster K1. Real-world performance will obviously vary depending on the task. But for applications that support parallel processing, this cluster board ...
Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More SiFive, a pioneer of processors based on RISC-V computing, unveiled its ...
The Government of India has announced the launch of the Linux-compatible DHRUV64 (VEGA AS2161) dual-core 64-bit RISC-V MPU ...
The new SiFive Performance P870-D continues the journey for the company from its regular P870, which had a six-wide out-of-order core with an RVA23 profile of the RISC-V instruction set architecture ...
Last month, a team of Google security researchers released a tool that can modify microcode of AMD's processors based on the Zen microarchitecture, the Zentool. While this is a security vulnerability, ...
Today, if you want to build a high-performance computing device, you can almost certainly find all the software you need in a free and open form. The same is not true for the processor chips that run ...
RISC-V is an open specification that allows an infinite number of implementations. But RISC-V goes beyond that and encourages processor architects to add new instructions to accelerate certain ...
Qualcomm has announced the acquisition of Ventana Micro Systems, a move aimed at strengthening its CPU portfolio through ...
SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste ...
In a previous post, we considered how you could create an optimized ISA for a domain-specific processor core by profiling software and experimenting with adding/removing instructions. Using the open ...
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